(A) Field of the Invention
The present invention relates to a method for reducing power consumption of an integrated circuit, and more specifically, to a low power gated and buffered clock network construction.
(B) Description of the Related Art
Clock signals are employed in VLSI system designs to synchronize the actions of the components of a design. Minimizing the clock skew and the clock power are of vital importance. The clock skew affects the maximum attainable frequency of operation and must be carefully controlled to ensure the correct functioning of the system. In addition, the clock net is a major source of power consumption in a system since it switches most frequently and it is a huge net that spans the entire chip with a large number of fanouts. Thus reducing the power consumption of the clock net can have a significant impact on the overall system power consumption.
Today power issue becomes more and more important because of the booming market of power critical devices such as portable electronic appliances and mobile devices. Since 30-50% of chip power is dissipated in the clock networks, researchers pay much attention to develop power reduction techniques for the clock network.
Clock gating is an effective power reduction technique for sequential circuits. The main idea is to temporarily turn off idle sub-circuits to save energy due to unnecessary switching. However, applying clock gating at the logical level and ignoring the physical placement of clock sinks may introduce unnecessary wiring and the increased power consumption due to the wiring can outweigh the saving from gating. Therefore, a gated clock tree construction algorithm must take logical as well as physical information into account.
Some works on gated clock tree construction considering both logical and physical information have been proposed. Unfortunately, there are a few shortcomings in these works. Some researches construct an initial zero-skew gated-clock tree but do not guarantee the final skew is zero after the refinement procedures, or only try to balance the number of gates and buffers between the source to sink paths but do not take wire delay into account to control the skew.
Therefore, it is necessary to construct a comprehensive gated and buffered clock network in which both the interconnect delay and the gate delay are taken into account, so as to minimize the clock power consumption.